A Jitter Variation according to Loop Filters in DLL
نویسندگان
چکیده
منابع مشابه
Analysis of Random Jitter in a Clock Multiplying DLL Architecture
In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitt...
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Under 500ps Yong-Bin Kim Tom Chen Department of Electrical Engineering Colorado State University Abstract This paper presents a variable delay line DLL circuit implemented in a 0.8 m CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The...
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ژورنال
عنوان ژورنال: Journal of the Institute of Electronics Engineers of Korea
سال: 2013
ISSN: 2287-5026
DOI: 10.5573/ieek.2013.50.12.033